1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to an apparatus and method for driving a liquid crystal display. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing the number of digital to analog converter integrated circuits and data carrier packages.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of the liquid crystal by using an electric field in displaying an image. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix form, and a driving circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, a plurality of gate lines and data lines are arranged in such a manner to cross each other. The liquid crystal cell is positioned at every area where the gate lines cross the data lines. The liquid crystal display panel is provided with a pixel electrode and a common electrode to apply an electric field to each of the liquid crystal cells. Each pixel electrode is connected to one of data lines through source and drain electrodes of a thin film transistor as a switching device. The gate electrode of the thin film transistor is connected to one of the gate lines allowing a pixel voltage signal to be applied to the pixel electrodes for each line.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel line by line. The data driver applies a data voltage signal to each of the data lines whenever the gate signal is applied to one of the gate lines. The common voltage generator applies a common voltage signal to the common electrode. Accordingly, the LCD controls light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with the data voltage signal for each liquid crystal cell, thereby displaying a picture. The data driver and the gate driver are integrated into a plurality of integrated circuits (IC's). The integrated data driver IC and gate driver IC are mounted on a tape carrier package (TCP) to be connected to the liquid crystal display panel by a tape automated bonding (TAB) system, or mounted on the liquid crystal display panel by a chip on glass (COG) system.
FIG. 1 schematically shows a data driving apparatus in a conventional LCD.
Referring to FIG. 1, the data driving apparatus includes data driving IC's 4 connected to a liquid crystal display panel 2 through TCP's 6, and a data printed circuit board (PCB) 8 connected to the data driving IC's 4 through the TCP's 6.
The data PCB 8 plays a role to receive various control signals from a timing controller (not shown), data signals and driving voltage signals from a power generator (not shown) and interface to the data driving IC's 4. Each of the TCP 6 is electrically connected to a data pad provided at the upper portion of the liquid crystal display panel 2 and an output pad provided at each data PCB 8. The data driving IC's 4 convert digital pixel data into analog pixel signals to supply to data lines on the liquid crystal display panel 2.
To this end, as shown in FIG. 2, each of the data driving IC's 4 includes a shift register part 14 for applying a sequential sampling signal, a latch part 16 for sequentially latching a pixel data VD in response to the sequential sampling signal and outputting the latched pixel data VD at the same time, a digital to analog converter (DAC) 18 for converting the latched pixel data VD from the latch part 16 into a pixel signal, and an output buffer part 26 for buffering and outputting the pixel signal from the DAC 18. Further, the data driving IC 4 includes a signal controller 10 for interfacing various control signals from a timing controller (not shown) and the pixel data VD, and a gamma voltage part 12 for supplying positive and negative gamma voltages required in the DAC 18. Each data driving IC 4 having a configuration as mentioned above drives n data lines D1 to Dn.
The signal controller 10 controls various control signals (i.e., SSP, SSC, SOE, REV, and POL, etc.) and the pixel data VD outputs to the corresponding parts. The gamma voltage part 12 further divides and outputs a plurality of gamma reference voltages generated from a gamma reference voltage generator (not shown) for each gray level.
There are n/6 shift registers included in the shift register part 14 sequentially shifting a source start pulse SSP from the signal controller 10 in response to a source sampling clock signal SSC to output as a sampling signal. The latch part 16 sequentially samples and latches the pixel data VD from the signal controller 10 by a certain unit in response to the sampling signal from the shift register part 14. To this end, the latch part 16 consists of n latches for latching n pixel data VD, each of which has a size corresponding to the bit number (i.e., 3 bits or 6 bits) of the pixel data VD. Particularly, the timing controller (not shown) simultaneously outputs the pixel data VD divided into even-numbered pixel data VDeven and odd-numbered pixel data VDodd through each transmission line so as to reduce the transmission frequency. Each of the even-numbered data VD even and the odd-numbered data VDodd includes red(R), green(G), and blue(B) pixel data. Thus, the latch part 16 simultaneously latches the even-numbered pixel data VDeven and the odd-numbered pixel data VDodd applied through the signal controller 10, that is, 6 pixel data for each sampling signal.
Subsequently, the latch part 16 simultaneously outputs n pixel data VD in response to a source output enable signal SOE from the signal controller 10. In this case, the latch part 16 restores the pixel data VD modulated in such a manner to have a reduced transition bit number in response to a data inversion selecting signal REV and then to output the restored pixel data VD having a reduced transition bit number. This is because the pixel data VD having a transited bit number greater than the reference value is supplied such that it is modulated to have a reduced transition bit number in order to minimize electromagnetic interference (EMI) upon data transmission from the timing controller.
The DAC 18 converts the pixel data VD from the latch part 16 into positive and negative pixel signals at the same time and outputs the converted pixel data VD. To this end, the DAC 18 includes a positive (P) decoding part 20 and a negative (N) decoding part 22 commonly connected to the latch part 16, and a multiplexor (MUX) 24 for selecting output signals of the P and N decoding parts 20 and 22.
There are n P decoders in the P decoding part 20 converting n pixel data simultaneously inputted from the latch part 16 into positive pixel signals by using positive gamma voltages from the gamma voltage part 12. Similarly, the N decoding part 22 having n N decoders simultaneously converts n pixel data inputted from the latch part 16 into negative pixel signals by using negative gamma voltages from the gamma voltage part 12. The multiplexor 24 responds to a polarity control signal POL from the signal controller 10 to selectively outputs the positive pixel signals from the P decoding part 20 or the negative pixel signals from the N decoding part 22.
The output buffer part 26 having n output buffers consists of voltage followers connected to the n data lines D1 to Dn in series. Such output buffers performs a buffering of the pixel voltage signals from the DAC 18 and supplies to the data lines D1 to Dn.
FIG. 3 illustrates a transmission path of a portion of the pixel data within the data driving IC 4 shown in FIG. 3.
In FIG. 3, latches 17 of the latch part 17 output 9 pixel data to 9 DAC's 19 constructing the DAC part 18 to convert the pixel data into pixel voltage signals. The pixel voltage signals are applied to the first to ninth data lines DL1 to DL9 through buffers 27 of the output buffer part 26.
As described above, each of the conventional data driving IC's 4 should have n DAC's, each of which includes a P decoder, an N decoder and a multiplexor, so as to drive n data lines DL1 to DLn. Thus, the data driving IC has a complex configuration causing a relatively high manufacturing cost. Accordingly, it is necessary to reduce the number of data driving IC's in order to lower a manufacturing cost.
In order to reduce the number of data driving IC's, there has been considered a scheme of increasing the number of data lines that can be driven by the data driving IC, that is, the number of output channels. However, since the number of DAC's having a complex configuration is increased in accordance with the increase in the number of driving channels of the data driving IC to enlarge a chip area, a cost of the TCP's proportional to the chip area is increased and their integration becomes difficult. As a result, manufacturing cost is increased and yield is likely to be reduced.